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| ASAHI KASEI [AKD5702-A] AKD5702-A AK5702 Evaluation Board Rev.1 GENERAL DESCRIPTION AKD5702-A is an evaluation board for the portable digital audio 16bit A/D converter with MIC-AMP, AK5702. AKD5702-A also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide AKD5702-A --- AK5702 Evaluation Board (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not support Windows NT.) FUNCTION * DIT with optical output * BNC connector for an external clock input * 10pin Header for serial control interface AVDD 3.0V Regulator DVDD VD AGND DGND Control Data 10pin Header LIN3/4/5 MIC3/4/5 RIN3/4/5 5V DSP 1 10pin Header LIN1/2/5 MIC1/2/5 RIN1/2/5 AK5702 TDM 10pin Header DSP 2 10pin Header EXT_MCLK EXT_LRCK EXT_BCLK CLOCK GEN AK4114 (DIT) Opt In Opt Out Figure 1. AKD5702-A Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual. 2007 / 04 ASAHI KASEI [AKD5702-A] Evaluation Board Manual Operation sequence 1) Set up the power supply lines. 1-1) When AVDD, DVDD and VD are supplied from the regulator. (Default) [REG] (Red) [AVDD] (Orange) [DVDD] (Orange) [VD] (Orange) [AGND] (Black) [DGND] (Black) = 5V = open (3.0V, supply from regulator, for AVDD of AK5702) = open (3.0V, supply from regulator, for DVDD of AK5702) = 2.7 3.6V (typ. 3.0V, for logic of digital part) = 0V (for analog ground) = 0V (for digital ground) 1-2) When AVDD, DVDD and VD are not supplied from the regulator. [REG] (Red) [AVDD] (Orange) [DVDD] (Orange) [VD] (Orange) [AGND] (Black) [DGND] (Black) = open = 2.4 3.6V (typ. 3.0V, for AVDD of AK5702) = 1.6 3.6V (typ. 3.0V, for DVDD of AK5702) = 2.7 3.6V (typ.3.0V, for logic of digital part) = 0V (for analog ground) = 0V (for digital ground) Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5702 and AK4114 should be reset once by bringing SW1, 2 "L" upon power-up. Evaluation mode In case of AK5702 evaluation using AK4114, same audio interface format should be set for both AK5702 and AK4114. About AK5702's audio interface format, refer to datasheet of AK5702. About AK4114's audio interface format, refer to Table 2 in this manual. Applicable Evaluation Mode (1) PLL Master Mode (Default) (2) PLL Slave Mode 1 (PLL Reference CLOCK: MCKI pin) (3) PLL Slave Mode 2 (PLL Reference CLOCK: BCLK or LRCK pin) (4) EXT Slave Mode (5) EXT Master Mode 2007 / 04 ASAHI KASEI [AKD5702-A] (1) PLL Master Mode (Default) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKO BCLK LRCK SDTOA VD GND GND NC NC SDTOB a) Set up jumper pins of MCKI clock When using X'tal as MCKI clock, X'tal of 11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz can be set to X1. X'tal of 11.2896MHz (Default) is set on the AKD5702-A. When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13MHz, 24MHz or 27MHz) is supplied through a BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XTI) and select EXT on JP7 (MCLK_SEL). JP12 (EXT) and R19 should be properly selected in order to match the output impedance of the clock generator. JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. b) Set up jumper pins of BCLK clock Output frequency (32fs/64fs) of BCLK should be set by "BCKO1-0 bit" in the AK5702. There is no necessity for set up JP9(BCLKFS). JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK BCLKFS 64fs 32fs c) Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs BNC_LRCK LRCKFS DIT DIT 2007 / 04 ASAHI KASEI [AKD5702-A] d) Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (2) PLL Slave Mode 1 (PLL Reference CLOCK: MCKI pin) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI BCLK LRCK SDTOA VD GND GND NC NC SDTOB a) Set up jumper pins of MCKI clock X'tal of 11.2896MHz (Default) is set on the AKD5702-A. In this case, the AK5702 corresponds to PLL reference clock of 11.2896MHz. In this evaluation mode, the output clock from MCKO pin of the AK5702 is supplied to a divider (U3: 74VHC4040), EXT_BCLK and EXT_LRCK clocks are generated by the divider. Then "MCKO bit" in the AK5702 should be set to "1". When an external clock is supplied through a BNC connector J1 (EXT_MCKI), select EXT_MCLK on JP16 (XTI) and select EXT on JP7 (MCKI_SEL). JP12 (EXT) and R19 should be properly selected in order too match the output impedance of the clock generator. JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs b) Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK 64fs 32fs BCLKFS DIT 2007 / 04 ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs d) Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (2-a) In the case of using AK4114. * In this mode, MCLK of AK5702 should be supplied from J1 (EXT_MCKI), and X1 should be open. This mode is BCLK=64fs, LRCK=1fs only. Set up jumper pins of MCKI clock JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL BNC_LRCK LRCKFS DIT JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK 64fs 32fs Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs BNC_LRCK LRCKFS DIT BCLKFS DIT 2007 / 04 ASAHI KASEI [AKD5702-A] Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (3) PLL Slave Mode 2 (PLL Reference CLOCK: BCLK or LRCK pin) * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. PORT4 MCKI BCLK LRCK SDTOA VD GND GND NC NC SDTOB a) Set up jumper pins of MCKI clock JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs b) Set up jumper pins of BCLK clock When an external clock is supplied through a BNC connector J2 (EXT/BCLK), J3 (EXT/LRCK), JP14 (EXT1) and R20, JP15 (EXT2) and R21 should be properly selected in order to much the output impedance of the clock generator. JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK BCLKFS 64fs 32fs DIT 2007 / 04 ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs d) Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (4) EXT Slave Mode * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. In this mode, MCKI, BCLK and LRCK should be supplied from PORT4. PORT4 MCKI BCLK LRCK SDTOA VD GND GND NC NC SDTOB a) Set up jumper pins of MCKI clock JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL BNC_LRCK LRCKFS DIT JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs b) Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK BCLKFS 64fs 32fs DIT 2007 / 04 ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs d) Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (4-a) In the case of using AK4114. *This mode is BCLK=64fs, LRCK=1fs only. The setting of JP16(XTI) is open, the clock of AK4114 use X'tal of X1. The signal of MCKO, BCLK and LRCK outputted from AK4114 is inputted into AK5702. Set up jumper pins of MCKI clock JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL BNC_LRCK LRCKFS DIT JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK 64fs 32fs BCLKFS DIT 2007 / 04 ASAHI KASEI [AKD5702-A] Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B (5) EXT Master Mode * Connect PORT4 (DSP1) with DSP. Figure below shows PORT4 pin assign. In this mode, MCKI should be supplied from PORT4, but BCLK and LRCK should not be supplied. PORT4 MCKI BCLK LRCK SDTOA VD GND GND NC NC SDTOB a) Set up jumper pins of MCKI clock JP16 XTI JP7 MCKI_SEL JP5 TDMMCLK_SEL JP32 MCLK_SEL BNC_LRCK LRCKFS DIT JP8 MKFS MCKO EXT_MCLK DIT EXT EXT_MCLK 384fs-768 MCKO EXT_MCLK 256fs 512fs 384/768fs MCKO 1024fs *The setting of JP8(MKFS) is invalid in this mode,but if JP8(MKFS) is open, the input of the buffer will be unstable. So JP8(MKFS) should set up any. b) Set up jumper pins of BCLK clock JP28 M/S JP9 BCLKFS JP10 BCLK_SEL M S 64fs-384 32fs-384 BNC_BCLK 64fs 32fs BCLKFS DIT 2007 / 04 ASAHI KASEI [AKD5702-A] c) Set up jumper pins of LRCK clock JP11 LRCKFS JP13 LRCK_SEL 2fs-384 1fs-384 2fs 1fs d) Set up jumper pins of SDTO JP30 SDTO_SEL JP29 SDTOB A B DIP Switch set up [SW1] (MODE): Mode Setting of AK4114 ON is "H", OFF is "L". No. 1 2 3 4 5 6 7 8 Name I2S M/S OCKS0 OCKS1 CAD1 CAD0 TEST I2C ON ("H") OFF ("L") AK4114 Audio Format Setting See Table 2 Master Clock Frequency Select See Table 3 Chip Address pin "L" p Control Mode Select pin "H": I2C, "L": 3-wire serial Table 1. Mode Setting Set up for AK4114 SW1 Resistor for AK5702 M/S 0 0 1 1 DIF1 DIF0 DIF1 DIF0 DAUX 1 0 0 0 24bit, Left justified Master 1 1 0 1 24bit, I2S Master 1 0 1 0 24bit, Left justified Slave 1 1 1 1 24bit, I2S Slave Table 2. Setting for AK5702 and AK4114 Audio Interface Format No. 0 2 OCKS1 0 1 OCKS0 0 0 MCKO1 256fs 512fs X'tal 256fs 512fs BNC_LRCK LRCKFS DIT Default Default Table 3. Master Clock Frequency Select for AK4114 (Stereo mode) 2007 / 04 ASAHI KASEI [AKD5702-A] Other jumper pins set up 1. JP1, JP3 (MPWRB) : Connect to MPWRB OPEN : No connect 9. JP35 (SDTOB_SEL) : Select input pin to TDMIN PDOWN : Connect to GND 12. JP38 (AVDD_SEL) : AVDD of the AK5702 REG : AVDD is supplied from the regulator ("AVDD" jack should be open). < Default > AVDD : AVDD is supplied from "AVDD " jack. 2007 / 04 ASAHI KASEI [AKD5702-A] 13. JP39 (DVDD_SEL) : DVDD of the AK5702 AVDD : DVDD is supplied from "AVDD". < Default > DVDD : DVDD is supplied from "DVDD " jack. 14. JP40 (LVC_SEL) DVDD VD : Supply line selection of Logic block of LVC. : Logic block of LVC is supplied from "DVDD". < Default > : Logic block of LVC is supplied from "VD " jack. The function of the toggle SW [SW2] (PDN): Power control of AK5702. Keep "H" during normal operation. [SW3] (DIT): Power control of AK4114. Keep "H" during normal operation. Keep "L" when AK4114 is not used. Indication for LED [LED1] (ERF): Monitor INT0 pin of the AK4114. LED turns on when some error has occurred to AK4114. Serial Control The AK5702 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (CTRL) with PC by 10-wire flat cable packed with the AKD5702-A Connect PC CSN CCLK CDTI AKD5702-A 10 Wire Flat Cable 10pin Connector 10pin Header Figure 2. Connect of 10 wire flat cable 2007 / 04 ASAHI KASEI [AKD5702-A] Analog Input / Output Circuits (1) Input Circuits a) LIN, RIN, MIC Input Circuit R24 (Open) J4 LIN125 JP17 2 3 1 LIN1 LIN2 LIN1 LIN2 LIN125_SEL LIN5 MR-552LS J5 MIC125 6 4 3 J6 RIN125 JP18 2 3 1 RIN1 RIN2 RIN1 RIN2 RIN125_SEL RIN5 MR-552LS JP19 LIN5_SEL LIN5 JP20 RIN5_SEL RIN5 R26 (Open) R25 (Open) J7 LIN345 JP21 2 3 1 LIN3 LIN4 LIN3 LIN4 LIN345_SEL LIN5 MR-552LS J8 MIC345 6 4 3 J9 RIN345 JP22 2 3 1 RIN3 RIN4 RIN3 RIN4 RIN345_SEL RIN5 MR-552LS R27 (Open) Figure 3. LIN, RIN, MIC Input Circuit AKM assumes no responsibility for the trouble when using the above circuit examples. 2007 / 04 ASAHI KASEI [AKD5702-A] 2. Control Software Manual Set-up of evaluation board and control software 1. Set up the AKD5702-A according to previous term. 2. Connect IBM-AT compatible PC with AKD5702-A by 10-line type flat cable (packed with AKD5702-A). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK5702 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD5702-A.exe" to set up the control program. Operation flow Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button Explanation of each buttons 1. [Port Reset]: 2. [Write default]: 3. [All Write]: 4. [Function1]: 5. [Function2]: 6. [Function3]: 7. [Function4]: 8. [Function5]: 9. [SAVE]: 10. [OPEN]: 11. [Write]: Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK5702. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation. Indication of data Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet. 2007 / 04 ASAHI KASEI [AKD5702-A] Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. 2. [Function1 Dialog] : Dialog to write data by keyboard operation Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal. If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. 3. [Function2 Dialog] : Dialog to evaluate IVOL There are dialogs corresponding to register of 18h and 19h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK5702 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK5702, click [OK] button. If not, click [Cancel] button. 2007 / 04 ASAHI KASEI [AKD5702-A] 4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". 2007 / 04 ASAHI KASEI [AKD5702-A] 5. [Function3 Dialog] The sequence of register setting can be set and executed. (1) Click [F3] Button. The following is displayed. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks". Figure 1. [F3] window 2007 / 04 ASAHI KASEI [AKD5702-A] 6. [Function4 Dialog] The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 2 opens. Figure 2. [F4] window 2007 / 04 ASAHI KASEI [AKD5702-A] 6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 3. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks") Figure 3. [F4] window (2) (2) Click [START] button, then the sequence is executed. 6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded. 6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change. 2007 / 04 ASAHI KASEI [AKD5702-A] 7. [Function5 Dialog] The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 4 opens. Figure 4. [F5] window 7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 5. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed. 2007 / 04 ASAHI KASEI [AKD5702-A] Figure 5. [F5] window (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded. 7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change. 2007 / 04 ASAHI KASEI [AKD5702-A] Revision History Date 2006/11/28 2007/04/09 Manual Revision KM086500 KM086501 Board Revision 0 1 Reason First Edition Error Correct Contents Circuit Change P2. Operation Sequence 1) Set up the power supply lines 1-1) Add (default) to the end of sentence. AVDD: open open (3.0V, supply from regulator, for AVDD of AK5702) DVDD: open open (3.0V, supply from regulator, for DVDD of AK5702) VD: for logic (typ 3.0V, for logic of digital part) 1-2) "REG" jack should be open open AVDD: for AVDD of AK5702 (typ.3.0V) (typ.3.0V, for AVDD of AK5702) DVDD: for DVDD of AK5702 (typ.3.0V) (typ.3.0V, for DVDD of AK5702) VD: for logic (typ 3.0V, for logic of digital part) P2. Evaluation Mode Applicable Evaluation Mode (1) Evaluation of PLL, Master Mode PLL Master Mode (2) Evaluation of PLL, Slave Mode PLL Slave Mode 1 (3) Evaluation of PLL, Slave Mode PLL Slave Mode 2 (4) Evaluation of EXT, Slave Mode EXT Slave Mode (5) EXT, Master Mode EXT Master Mode P3-P10 (1) Evaluation of PLL, Master Mode PLL Master Mode a) Set up jumper pins of MCKI clock (J1: EXT_MCKI) J1 (EXT_MCKI) JP8 JP8 (MKFS) b) Set up jumper pins of BCLK clock JP9 JP9 (BCLKFS) (2) Evaluation of PLL, Slave Mode PLL Slave Mode 1 a) Set up jumper pins of MCKI clock (J1: MCLK_SEL) J1 (EXT_MCKI) (2-a) In the case of using AK4114 J1 J1 (EXT_MCLK) JP8 JP8 (MKFS) (3) Evaluation of PLL, Slave Mode PLL Slave Mode 2 (4) Evaluation of EXT, Slave Mode EXT Slave Mode Connect PORT4 (DSP1) with DSP In this mode, BCLK and LRCK should be supplied from PORT4, but MCKI should not be supplied. In this mode, MCKI, BCLK and LRCK should be supplied from PORT4. (4-a) In the case of using AK4114 JP16 JP16 (XTI) JP8 JP8 (MKFS) (5) EXT, Master Mode EXT Master Mode a) Set up jumper pins of MCKI clock JP8 JP8 (MKFS) b) Set up jumper pins of BCLK clock The direction of jumper setup of JP28 (M/S): S (Slave) M (Master) P11. Other jumper pins set up 12. JP38 (AVDD_SEL) OPEN REG SHORT AVDD Resistance value, Capacitance Value Change: MCKI: R13: 51 R100:100, C100: Open 22p BICK: R101: Short 100, C101: Open 22p LRCK: R102: Short 100, C102: Open 22p 2007 / 04 ASAHI KASEI [AKD5702-A] IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. 2007 / 04 A B C D E RIN3 RIN4 RIN5 RIN1 LIN3 LIN4 LIN5 CN4 32pin_4 E E 32 31 30 29 28 27 26 R1 R2 R3 R5 (open) (open) 2.2k 2.2k JP1 JP3 MPWBR MPWBR 2 2 2 2 2 2 2 2 25 LIN1 JP2 JP4 MPWAR MPWAR R4 R6 R7 2.2k 2.2k (open) (open) D 1 1 1 1 1 1 1 D 31 29 27 32 30 28 U1 RIN3 RIN4 RIN5 RIN1 LIN3 LIN4 LIN5 26 LIN1 25 1 1u 1u 1u 1u 1u 1u 1u CN1 1 2 1 MPWRB RIN2 24 1 + 2.2u C11 0.1u C12 2 VCOM LIN2 23 1 + 2 1 R9 PDN 3 51 3 PDN MPWRA 22 R10 CAD0 C 51 4 CAD0 VCOC 21 4 DVDD 5 1 + C15 10u C16 0.1u 6 6 VSS2 VSS1 19 C17 0.1u C18 + 10u 2 19 R101 5702_LRCK 7 100 7 LRCK I2C 18 2 1 5 DVDD AK5702 R102 5702_BCLK 8 100 C101 22p 8 BCLK SDTOB SDTOA TDMIN MCKO CCLK TEST CDTI CSN MCKI 17 32pin_1 C102 22p 9 10 11 12 13 14 15 B 16 R14 51 R15 51 R16 (short) R17 51 9 10 11 12 13 14 15 A CN2 32pin_2 5702_TDMIN CDTI/SDA 5702_MCKO CCLK/SCL 5702_SDTOB 5702_SDTOA CSN/CAD1 TEST 16 A B C + + + + + + + + + + + + + + C1 C2 C3 C4 C5 C6 C7 C8 1u R8 + + + CN3 C9 1u 2 24 RIN2 C10 1u 2 23 LIN2 C13 (open) R11 10k C14 22 21 4.7n C AVDD 20 20 AVDD R12 51 18 I2C R100 100 17 5702_MCKI C100 22p 32pin_3 B R18 51 A Title Size Document Number AKD5702-A AK5702 Sheet E Rev A3 Date: D 1 1 of Monday, April 09, 2007 6 A B C D E E E VD D D EXT_MCLK 384fs-768 JP5 EXT_MCLK JP6 TDMMCLK_SEL 256fs 128fs JP8 4114_MCKO J1 EXT_MCKI C TDMBCLK_SEL U3 10 11 CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1 DIT EXT JP7 4 3 2 1 10 11 12 13 14 7 U2 1PR 1CK 1D 1CLR 2PR 2CK 2D 2CLR VCC GND 1Q 1Q 2Q 2Q 5 6 9 8 256fs 512fs 1024fs 384/768fs MCKO MKFS 64fs-384 32fs-384 64fs 32fs JP9 4114_BICK DIT BCLKFS BNC_BCLK JP10 EXT_BCLK MCKI_SEL BCLKFS 4114_LRCK BCLK_SEL C 2 3 4 5 1 16 VDD R19 51 C19 JP12 EXT 0.1u 8 C20 0.1u MCKO VSS 74AC74 74HC4040 2fs-384 1fs-384 2fs 1fs JP11 DIT LRCKFS BNC_LRCK JP13 EXT_LRCK LRCKFS LRCK_SEL U4 1 9 10 7 2 3 4 5 6 16 8 CLR RCO LOAD QA ENT QB ENP QC CLK QD A B C D VCC GND 15 14 13 12 11 J2 EXT_BCLK U5 1 3 5 9 11 13 14 7 1A 2A 3A 4A 5A 6A VCC GND 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 2 3 4 5 1 R20 51 JP14 EXT B B C21 0.1u 74AC163 C22 0.1u 74HCU04 J3 EXT_LRCK 2 3 4 5 1 R21 51 JP15 EXT A A Title Size Document Number AKD5702-A CLOCK Sheet E Rev A3 Date: A B C D 1 2 of Monday, April 09, 2007 6 A B C D E L1 PORT1 VCC GND OUT E 1 3 2 1 2 VD C23 0.1u (short) TORX141 E R22 2 C24 10u 1 470 DVDD VD VD C25 0.1u + C26 0.47u I2S M/S OCKS0 OCKS1 CAD1 CAD0 TEST I2C SW1 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 R23 18k 45 41 39 47 43 48 46 44 42 40 38 VCOM AVSS R TEST1 AVDD NC NC D INT1 RX3 RX2 RX1 RX0 37 U6 D SW DIP-8 1 IPS0 INT0 36 INT0 2 NC OCKS0 35 OCKS0 RP1 9 8 7 6 5 4 3 2 1 3 DIF0 OCKS1 34 OCKS1 OCKS0 OCKS1 CAD1 CAD0 TEST I2C 4 TEST2 CM1 33 5 DIF1 47k C 6 NC AK4114 CM0 32 VD JP16 XTI EXT_MCLK MCKO C PDN 31 4114_PDN C27 5p DIF2 XTI 1 7 30 X1 11.2896MHz IPS1 XTO 2 8 29 C28 5p 9 P/SN DAUX 28 DAUX 10 XTL0 MCKO2 27 11 B XTL1 BICK 26 4114_BICK B 12 VIN MCKO1 DVDD COUT UOUT BOUT VOUT DVSS DVSS TVDD LRCK TX0 TX1 SDTO 25 13 14 15 16 17 18 19 20 21 22 23 C29 0.1u + C30 0.1u + 1 2 1 2 C31 10u VD VD C32 10u 4114_MCKO A IN VCC GND 3 2 1 4114_LRCK PORT2 VD C33 0.1u 24 A TOTX141 Title Size Document Number AKD5702-A DIT Sheet E Rev A3 Date: A B C D 1 3 of Monday, April 09, 2007 6 A B C D E R24 (Open) E E J4 LIN125 2 3 1 JP17 LIN1 LIN2 LIN1 LIN2 LIN125_SEL LIN5 MR-552LS J5 MIC125 6 4 3 D J6 RIN125 2 3 1 JP18 RIN1 RIN2 RIN1 RIN2 D RIN125_SEL RIN5 MR-552LS JP19 LIN5_SEL LIN5 JP20 RIN5_SEL RIN5 R26 (Open) C C R25 (Open) LIN3 J7 LIN345 2 3 1 JP21 LIN4 LIN345_SEL LIN5 LIN3 LIN4 MR-552LS J8 MIC345 6 4 3 RIN3 B J9 RIN345 2 3 1 JP22 RIN4 RIN345_SEL RIN5 RIN3 RIN4 B MR-552LS R27 (Open) A A Title Size Document Number AKD5702-A Input Sheet E Rev A3 Date: A B C D 1 4 of Monday, April 09, 2007 6 A B C D E U7 EXT_BCLK 3 A1 B1 21 5702_BCLK LVC EXT_LRCK 4 A2 B2 20 5702_LRCK C34 0.1u 14 13 12 11 9 7 8 E E 5 A3 B3 19 6 A4 B4 18 10 GND VCC 4B 4A 4Y 3B 3A 3Y R28 (open) MCKO BCLK LRCK SDTO VCC PORT3 1 2 3 4 5 10 9 8 7 6 7 A5 B5 17 8 A6 B6 16 U8 15 7 6 5 4 3 2 1 RP2 1A 1B 1Y 2A 2B R-PACK6R VD JP28 2 1 VCCA VCCB 24 R-PACK6R LVC 1 2 3 4 5 PORT4 D DIR VCCB 23 MCKI 1 BCLK 2 LRCK 3 SDTOA4 5 VD 10 9 8 7 6 M/S C35 0.1u 11 GND OE 22 C36 0.1u 6 2Y 7 6 5 4 3 2 1 RP3 74LVC32 DSP2 9 A7 B7 10 A8 B8 14 D SDTOB 12 DSP1 R29 10k VD JP29 SDTOB GND GND 13 U10 74AVC8T245 MCKO JP30 DAUX 3 A1 B1 21 5702_MCKO 4 JP32 SDTO_SEL MCLK_SEL U9 5 3 21 A2 B2 20 A3 B3 19 EXT_MCLK MCKI1 BCLK2 LRCK3 4 TDMIN VD 5 C A1 B1 5702_MCKI 6 PORT5 10 9 8 7 6 4 A2 B2 20 7 19 A4 B4 18 A5 B5 17 5 TDM JP35 SDTOB R30 (open) VD JP36 I2C 7 6 A3 B3 5702_TDMIN 8 A6 B6 16 C 5702_SDTOB TDMIN P_DOWN SDTOB_SEL CAD1 R31 R33 R35 10k 10k 10k A4 B4 18 9 17 A7 B7 15 5702_SDTOA VD R32 R34 R36 470 470 470 3-WIRE CTRL_SEL 8 A5 B5 CSN/CAD1 10 A8 B8 14 CDTI/SDA A6 B6 16 CCLK/SCL VD 1 VCCA VCCB 24 R37 100k 1 2 3 4 5 9 PORT6 10 9 8 7 6 A7 B7 15 LVC CSN/CAD1 CCLK/SCI CDTI/SDA CDTO/SDA(ACK) 2 R38 (short) 10 A8 B8 14 DIR VCCB 23 PDN C37 0.1u 11 GND OE 22 C38 0.1u CTRL VD 1 VCCA VCCB 24 LVC 12 GND GND 13 2 DIR VCCB 23 B C39 0.1u VD K 11 GND OE 22 C40 0.1u 74AVC8T245 B A D1 HSU119 R39 10k 12 GND GND 13 L 3 1 H SW2 PDN 2 74AVC8T245 C41 0.1u 1 3 5 9 11 13 R40 1k U11 1A 2A 3A 4A 5A 6A VCC GND 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 VD VD VD 0.1u 14 C42 7 K 74LVC07 D2 HSU119 R41 10k INT0 1 3 5 9 11 13 14 7 U12 1A 2A 3A 4A 5A 6A VCC GND 1Y 2Y 3Y 4Y 5Y 6Y 2 4 6 8 10 12 A PDN R42 1k K LED1 ERF A A VD 4114_PDN A 3 1 L H C43 0.1u C44 0.1u SW3 4114_PDN 2 74HC14 Title Size Document Number AKD5702-A LOGIC Sheet Rev A2 Date: A B C D E 1 5 of Monday, April 09, 2007 6 A B C D E E T1 REG_IN TA48M03F IN GND OUT 1 JP37 GND REG1 T45_R AVDD1 T45_O 1 E DVDD1 T45_O 1 VD1 T45_O 1 AGND1 DGND1 T45_BK T45_BK 1 1 C47 0.1u 2 C45 0.1u C46 + 47u REG_IN AVDD1 1 DVDD1 VD1 TP1_AGND1 AVDD1 L2 1 1 2 TP1_DGND1 REG AVDD1 JP38 AVDD TP2_AGND1 TP2_DGND1 D C48 D + 2 (short) AVDD_SEL TP3_AGND1 TP3_DGND1 47u AVDD JP39 L3 1 1 2 DVDD1 AVDD DVDD R43 DVDD 5.1 C49 47u C + 2 (short) DVDD_SEL C JP40 VD1 1 L4 (short) 2 DVDD VD LVC_SEL LVC C50 47u 1 + 2 VD B B A A Title Size Document Number AKD5702-A POWER Monday, April 09, 2007 E A3 Date: A B C D Rev 1 Sheet 6 of 6 |
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